Semiconductor memory devices or solid-state drives (SSD) and controllers thereof typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even without power, as opposed to volatile memory, which requires power to maintain the stored information.
The semiconductor devices may be configured to include blocks (or groups, or groups of blocks referred to herein as jumbo blocks) of single-level cell (SLC) non-volatile memory units and/or multi-level cell (MLC) (e.g., dual-level, triple-level, quad-level, or any other non-single level cell) memory units. There are performance tradeoffs with each type of memory cell. For example, MLCs store more data per cell than SLCs, but MLCs degrade more quickly and have longer read times for data requests. In some instances, to conserve memory space, the semiconductor devices may transfer data from a set of SLC blocks to a single MLC block. The semiconductor devices may be configured to conduct X2 or higher programming on a set of SLC blocks by using a folding operation/process (e.g., on-chip copy operation or copy through controller operation). In a folding process, a set of SLC blocks which have a high validity count may be selected for folding to the target MLC block. As part of the folding process, the SLC partition data may be moved to the MLC block to make space for the next set of host writes. However, subsequent reads after the background operation may suffer since the host read may be directed to the MLC blocks instead of the SLC blocks, which are inherently faster for memory reads than MLC blocks.
Thus, there is a need for an efficient semiconductor device and controller thereof that optimize use of all blocks in the memory in the most efficient manner.